The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A FET includes a gate electrode as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes.
An important parameter associated with MOS transistors is the device resistance (“on resistance”) from source to drain when the device is turned on. The total on resistance is the sum of the channel resistance plus the external resistance. The channel resistance is a function of the mobility of majority carriers in the device channel; other parameters being equal, the higher the mobility, the lower the channel resistance. The external resistance includes a number of components including but not limited to the resistance through each of the source and drain regions and the contact resistance to the source and drain regions. It is known to enhance the mobility of majority carriers by applying a strain to the channel region. A compressive longitudinal strain enhances the mobility of majority carrier holes in the channel of a P-channel MOS (PMOS) transistor and a tensile longitudinal strain enhances the mobility of majority carrier electrons in the channel of an N-channel MOS (NMOS) transistor. Such channel strains can be induced by embedding a strain inducing monocrystalline material into the source and drain regions of the transistor. It is also known to reduce the external resistance including the resistance through the source and drain regions and the contact resistance to the source and drain regions by forming a metal silicide layer contacting the source and drain regions. Unfortunately, the formation of a metal silicide layer on the source and drain regions has the side effect of causing a relaxation of the strain on the channel region caused by the embedded material. Siliciding the source and drain regions to reduce the external resistance thus may negate the possible reduction in channel resistance achieved by embedding a strain inducing material.
Accordingly, it is desirable to provide a strain enhanced semiconductor device having an optimized total on resistance. In addition, it is desirable to provide methods for fabricating a strain enhanced semiconductor device having low on resistance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.